(a) Field of the Invention
The present invention relates to a semiconductor, and more specifically to a metal-insulator-metal (MIM) capacitor and a method of manufacturing the MIM capacitor.
(b) Discussion of the Related Art
Generally, a capacitor used in memory cells includes a lower storage electrode, a dielectric layer and an upper plate electrode. Known techniques for increasing capacitance include: decreasing a thickness of the dielectric layer; increasing the effective surface through three dimensional capacitor structures; and using a dielectric layer having a high dielectric constant, such as TaO2 or Al2O3. When TaO2 is used in the dielectric layer, the capacitor has a MIS (Metal-Insulator-Semiconductor) or MIM (Metal-Insulator-Metal) structure with a metal upper electrode.
However, when the MIS structure capacitor uses TaO2 or Al2O3 in the dielectric layer, a thickness of the dielectric layer increases. The increased thickness is caused by oxidation of polysilicon during a thermal treatment process performed at high temperature after the formation of the dielectric layer. Therefore, the capacitance of the MIS capacitor is reduced as the dielectric layer is made thicker. For these reasons, the MIM structure is often preferred over the MIS structure.
A method of manufacturing a related art MIM structure capacitor is explained with reference to FIG. 1.
As shown in FIG. 1, a lower metal layer is deposited on a semiconductor substrate 10 and photolithographically patterned to form a lower electrode 11. Then an insulating layer having a high dielectric constant and an upper metal layer are deposited, in this order, to cover the lower electrode 11. The upper metal layer and the insulating layer are patterned to form an upper electrode 13 and a dielectric 12 by a photolithography process, to expose portions of both sides of the lower electrode 11. This process results in the formation of the capacitor 100, having the MIM structure.
However, in the related art MIM structure, the lower electrode 11 is partially etched during the formation of the dielectric 12 and the upper electrode 13. Therefore, it is probable that re-deposition of the lower metal occurs on side surfaces of the dielectric 12 and the upper electrode 13, which may result in an electric shorts between the lower and upper electrodes 11 and 13.
Further, the lower electrode 11 is longer than the upper electrode 13, and thus the lower electrode 11 has exposed side surfaces. Therefore, at the side area parasitic capacitance can result, and the characteristics of the MIM capacitor may be degraded.